Integration of IEEE 1149.1 with mixed ECL, TTL and differential logic signals

IEEE 1149.1, the Standard Test Access Port and Boundary-Scan Architecture, has been most often applied to TTL-compatible logic circuits. This paper reviews some issues which arise when applying 1149.1 to systems fabricated with integrated circuits (IC´s) from mixed, incompatible logic families such as emitter coupled logic (ECL) and TTL-compatible logic; and interconnection systems where, to improve performance, the logic value is represented as the difference in potential between two conductors