Implementing BIST and boundary-scan in a digital signal processor ASIC for radiocommunication applications

Author

Pichon, Francis

Author_Institution

Thomson-CSF, Gennevilliers, France

fYear

1993

fDate

19-22 Apr 1993

Firstpage

361

Lastpage

369

Abstract

This paper describes the testability strategy used in the design of a complex DSP VLSI for radiocommunication applications. A solution based on the use of a micro-coded BIST has been chosen. The IEEE 1149.1 boundary scan test is used to control the chip self-test. The BIST structures provide go/no-go flags as well as diagnosis capabilities using signature analysis

Keywords

VLSI; application specific integrated circuits; automatic test equipment; boundary scan testing; built-in self test; computer architecture; design for testability; digital signal processing chips; electronic equipment testing; logic testing; production testing; transceivers; BIST; DSP VLSI; IEEE 1149.1; JTAG; RAM; ROM; boundary-scan; chip self-test; digital signal processor ASIC; go/no-go flags; handset radio transceiver; micro-coded BIST; radiocommunication; signature analysis; testability strategy; Application specific integrated circuits; Automatic testing; Built-in self-test; Digital signal processing chips; Digital signal processors; Filtering; Finite impulse response filter; Signal design; Signal processing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246576

Filename

246576