Influence of IC synthesis on the random pattern testability of parametric bridging faults

Author

Dalpasso, M. ; Favalli, M. ; Olivo, P. ; Riccò, B.

Author_Institution

Bologna Univ., Italy

fYear

1993

fDate

19-22 Apr 1993

Firstpage

398

Lastpage

407

Abstract

The quality of synthesis schemes and of macro-gate libraries as well as of design-for-testability approaches can also be decided by means of testability measures performed on the final or even intermediate design. Such an approach is significantly improved by outlining a method to include within the fault set the parametric bridging faults internal to macro-gates, that model many defects actually present in CMOS circuits. The presented scheme exploits the separation between local and global fault detection for such faults, extending the testability measures for random testing via the key definition of random detection probability for a bridging fault. Different macro-gate libraries are compared by means of such testability measures performed on well-known benchmark circuits

Keywords

CMOS integrated circuits; VLSI; design for testability; fault location; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; probability; random processes; CMOS circuits; IC synthesis; benchmark circuits; design-for-testability; global fault detection; local fault detection; logic design; macro-gate libraries; parametric bridging faults; random detection probability; random pattern testability; random testing; Benchmark testing; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Integrated circuit synthesis; Integrated circuit testing; Libraries; Performance evaluation; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

European Test Conference, 1993. Proceedings of ETC 93., Third

Conference_Location

Rotterdam

Print_ISBN

0-8186-3360-3

Type

conf

DOI

10.1109/ETC.1993.246583

Filename

246583