Analysis and optimization of sequential circuit element to combat single-event timing upsets

This paper presents the analysis and optimization of a flip-flop while considering the effect of energetic particle hits on its setup and hold times. First it is shown that the particle hit tightens the setup and hold timing constraints imposed on the flip-flop. Next it is shown how to size transistors of a clocked master-slave CMOS flip-flop to make it more robust against single-event timing upsets. Experimental results to assess the effectiveness of transistor sizing step are provided and discussed.