Using EDIF in IC testing: experience from the Everest project

Without a standard for describing test vectors, timing and levels it is a cumbersome process to take test data from an ATPG to a simulator or from a simulator to an ATE. From the electronic industries in Europe, USA and Japan, many people have worked together under the auspices of the EIA to create a provisional test view in EDIF (electronic design interchange formats). This paper evaluates an early version (i.e. EDIF 2 0 31) of this standard both from a software developer´s view and from a user´s view via a large scale benchmark performed by the Everest project