Title :
Digital enhancement of frequency synthesizers
Author :
Ouda, Mahmoud ; Hegazi, Emad ; Ragai, Hany F.
Author_Institution :
Dept. of Electron. & Commun., Ain Shams Univ., Cairo, Egypt
fDate :
May 30 2010-June 2 2010
Abstract :
In this paper, we propose an All-Digital On-Chip Phase Noise Measurement Technique. This Technique can be integrated as part of a built-in self-test (BIST) scheme for phase-locked loop (PLL)-based clock synthesizers. The proposed technique based on an all digital ΣΔ-frequency discriminator. Unlike all previously reported techniques, our proposed technique is implemented using digital-only circuits and can report digital numbers corresponding to the close in phase noise level of the PLL to a digital BIST controller. This makes it easily integrated and scaled down for high-density microprocessor applications with modern sub 100nm technology nodes.
Keywords :
built-in self test; clocks; frequency synthesizers; microprocessor chips; noise measurement; phase locked loops; phase noise; BIST scheme; PLL-based clock synthesizers; all-digital ΣΔ-frequency discriminator; all-digital on-chip phase noise measurement technique; built-in self-test scheme; digital BIST controller; digital enhancement; frequency synthesizers; high-density microprocessor applications; phase noise level; phase-locked loop; Clocks; Frequency synthesizers; Integrated circuit measurements; Jitter; Noise measurement; Phase frequency detector; Phase locked loops; Phase measurement; Phase noise; Semiconductor device measurement; All digital PLL (AD-PLL); Jitter; PLL; phase domain; phase noise; sigma delta frequency discriminator (ΣΔFD); voltage-controlled oscillator (VCO);
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537384
