DocumentCode
3378870
Title
Resynthesis for testability of redundant combinational circuits
Author
Evans, Allison H. ; Macii, Enrico
Author_Institution
Dept. of Comput. Sci., California Univ., La Jolla, CA, USA
fYear
1993
fDate
19-22 Apr 1993
Firstpage
511
Lastpage
512
Abstract
This paper presents an algorithm to generate circuits which are irredundant for stuck-at fault testing but which preserve all the properties of the original design; then any state-of-the-art ATPG procedure can be applied to the modified network. The algorithm makes use of additional control inputs to convert the redundant AND-OR function of the circuit, represented as the sum of all its prime implicants, into the irredundant one
Keywords
combinatorial circuits; design for testability; logic design; logic testing; production testing; redundancy; ATPG; PLA; logic testing; modified network; redundant AND-OR function; redundant combinational circuits; resynthesis; stuck-at fault testing; testability; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Circuit testing; Combinational circuits; Computer science; Electrical fault detection; Input variables; Logic circuits; Logic functions;
fLanguage
English
Publisher
ieee
Conference_Titel
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location
Rotterdam
Print_ISBN
0-8186-3360-3
Type
conf
DOI
10.1109/ETC.1993.246606
Filename
246606
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