Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs

The TDDB failure mechanism of high-k dielectric/metal gate (HK/MG) CMOSFETs on DC and AC stress conditions are investigated in comparison to poly-Si/SiON. All devices under unipolar AC stress exhibit longer failure time (t_bd) as frequency increases. In case of HK/MG, the SILC behavior has been attributed to the bulk transient charge trapping by pre-existing defects in HK. Since trapped charges in HK can easily be detrapped once a relaxation bias is applied, t_bd is increased as frequency becomes higher. Unlike unipolar AC bias condition, HK/MG nMOSFETs with bipolar AC stress exhibit shorter t_bd than with DC at a lower frequency. This is attributed to hole trapping into IL as V_g is at the gate injection bias since HK/MG stack has higher probability of electron injection than poly-Si/SiON due to relatively lower barrier height. However, bipolar AC TDDB in high frequency shows longer t_bd than DC TDDB because of lack of time to generate enough holes in the IL. In bipolar AC bias condition, the higher power-law time exponent (n) appears because G_m degradation by hole generation is aggravated at the gate injection bias in nMOSFET, while pMOSFET SILC is generated by bulk charge trapping at the substrate injection bias.