Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path

Size of STI wells is another significant factor to affect the stress magnitude (device mobility) besides size of transistor active regions. In this paper, we present a technique for improving device mobility in the critical path via global STI well width adjusting following the chip placement stage. The methodology formulates the original device mobility enhancement problem as a series of convex geometric programs(GP), which is based on two observations that: (1)Minimum layout perturbation objective could be reached when introducing into an iterative GP approximation procedure; (2)Terms in charge of PMOS channel mobility optimization could be modeled as posynomials of design variables, that is, the width of STI wells. Finally, by applying the presented technique to several IBM-PLACE benchmarks, and solving the resulted GP problems by a GP solver named MOSEK, we are able to demonstrate its effectiveness.