Title :
Interconnection effects in Package on Package design
Author :
Pulici, P. ; Candela, G. ; Campardo, G. ; Vanalli, G.P. ; Stoppino, P.P. ; Losavio, A. ; Lessio, T. ; Dellutri, M. ; Guarnaccia, D. ; Iacono, F. Lo
Author_Institution :
Politec. di Milano, Milan
Abstract :
The PoP (Package on Package) design procedure is described in this paper, focusing principally on the constraints and the system characteristics. The PoP structure is more and more diffused because it increases the customer flexibility and the final yield by means of a separate testing of Top and Bottom devices. In this paper, a Top PoP design, composed by two stacked memory dice (a NOR Flash and a SDRAM), is described pointing out the electrical package impact. The memory PoP has to be accessed up to 250 Mb/s. Such a frequency involves the package to be designed basing on some rules and evaluating its electrical impact by means of a signal integrity flow.
Keywords :
DRAM chips; NOR circuits; SRAM chips; flash memories; integrated circuit design; integrated circuit interconnections; system-in-package; NOR flash memory; SDRAM; electrical package impact; interconnection effects; package on package design procedure; signal integrity flow; stacked memory dice; Clocks; Delay effects; Frequency; Packaging; Performance analysis; Power supplies; SDRAM; Signal analysis; Testing; Timing;
Conference_Titel :
Signal Propagation on Interconnects, 2007. SPI 2007. IEEE Workshop on
Conference_Location :
Genova
Print_ISBN :
978-1-4244-1223-5
Electronic_ISBN :
978-1-4244-1224-2
DOI :
10.1109/SPI.2007.4512239
