DocumentCode :
3379105
Title :
Whitespace insertion for through-silicon via planning on 3-D SoCs
Author :
Zhong, Wei ; Chen, Song ; Yoshimura, Takeshi
Author_Institution :
Grad. Sch. of Inf. Production & Syst., Waseda Univ., Kitakyushu, Japan
fYear :
2010
fDate :
May 30 2010-June 2 2010
Firstpage :
913
Lastpage :
916
Abstract :
As technology advances, 3-D ICs can significantly alleviate the interconnect problem coming with the decreasing of feature size and are promising for heterogeneous integration. In 3-D ICs, one of the key challenges is the vertical technology, using through-silicon via (TSV) for different device layers connection. In this paper, by noticing the TSV assignment comes under the influence of the whitespace distribution in a given 3-D floorplan, we proposed an algorithm called whitespace insertion (WSI) based on the floorplan-representation Sequence Pair to make the whitespace distribution in the given floorplan more reasonable for TSV insertion. When given 3-D circuit placement or floorplan results, we also proposed a minimum spanning tree based algorithm for TSV assignment to minimize the total wire length, assuming each net may have at most one TSV on each device layer. Experimental results show that, in the given 3-D floorplans there is a huge gap about 45.54% of the wire length increase between the ideal and the practice. And based on our method, the total wire length can be reduced by 13% on average without changing the chip area.
Keywords :
integrated circuit layout; system-on-chip; 3D SoC; 3D floorplan; floorplan-representation sequence pair; heterogeneous integration; minimum spanning tree based algorithm; through-silicon via planning; whitespace insertion; Delay; Integrated circuit interconnections; Production planning; Production systems; Routing; Technology planning; Temperature; Through-silicon vias; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
Type :
conf
DOI :
10.1109/ISCAS.2010.5537404
Filename :
5537404
Link To Document :
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