Title :
Modelling delay in symbolic test for data paths with partial scan
Author :
Steensma, Johannes ; Catthoor, Francky ; De Man, Hugo
Author_Institution :
IMEC, Leuven, Belgium
Abstract :
The problem of handling (pipeline) delay in data paths using a symbolic test methodology is addressed. The authors show that the delay in the incomplete scan path architecture, where only a subset of the registers is included in the scan path in order to eliminate the feedback loops, can be easily modelled and taken into account in the (combinational) symbolic test pattern generator. The pith of the methodology is formed by novel controllability and observability descriptions
Keywords :
boundary scan testing; combinatorial circuits; controllability; delays; logic testing; observability; boundary scan; combinational test pattern generation; controllability; data paths; incomplete scan path; observability; partial scan; pipeline delay; symbolic test; Circuits; Clocks; Controllability; Delay; Feedback loop; Flip-flops; Observability; Pipeline processing; Test pattern generators; Testing;
Conference_Titel :
European Test Conference, 1993. Proceedings of ETC 93., Third
Conference_Location :
Rotterdam
Print_ISBN :
0-8186-3360-3
DOI :
10.1109/ETC.1993.246622
