Semicustom power gating design

Sub threshold leakage current has increased dramatically with technology scaling and it consumes a significant portion of the total power. In order to reduce the leakage current, one of the efficient method is power gating. The main challenge in power gating is, to design switching fabric and power controller. In this paper the main aim is to implement power gating in semicustom design. For this we implement a power controller for the design, insert sleep transistors and size the sleep transistors. According to the input, the power controller generates the signal to decide which block is to turn ON and which one is to turn OFF. The switching transistors such as header or footer are inserted in to the design, which act as switches. Sizing of the sleep transistors is essential in order to reduce the long wake up delays. The proposed methodology is applied to 8 bit RISC architecture by using Design Architect from MENTOR GRAPHICS with the modified ADK library.