A new MOSFET hot carrier model in SPICE feasible for VLSI reliability analysis

Author

Chung, Steve S. ; Hsu, P.-C. ; Lee, J.-S.

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1991

fDate

22-24 May 1991

Firstpage

283

Lastpage

287

Abstract

A newly-developed SPICE-compatible submicron LDD MOS transistor model for simulating the hot electron effect in VLSI circuit is proposed. It includes a consistent DC (I-V) and hot electron induced degradation model. Experiment measurement, parameter extraction and optimization were performed to obtain a new set of drain- and substrate-current under both DC- and AC-stress conditions. Incorporation of the above model equations in SPICE has been made. In addition, hot electron induced degradation effect and the reliability analysis in a circuit simulation environment are demonstrated with practical examples

Keywords

SPICE; VLSI; circuit analysis computing; circuit reliability; hot carriers; insulated gate field effect transistors; semiconductor device models; semiconductor process modelling; MOSFET hot carrier model; SPICE-compatible; VLSI reliability analysis; circuit simulation environment; hot electron effect; model equations; parameter extraction; reliability analysis; submicron LDD MOS transistor model; Circuit simulation; Degradation; Electrons; Equations; Hot carriers; MOSFET circuits; Parameter extraction; Performance evaluation; SPICE; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246664

Filename

246664