DocumentCode :
3379494
Title :
Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU
Author :
Trieu, Minh Thien ; Hoang, Huong Thien ; Vo, Phong The ; Vo, Hung Bao ; Yuyama, Yoichi
Author_Institution :
Renesas Design Vietnam Co. Ltd., Ho Chi Minh City, Vietnam
fYear :
2011
fDate :
25-28 Oct. 2011
Firstpage :
39
Lastpage :
42
Abstract :
We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core [1] while still keeping it co-operates with CPU core. As a result, 97% flip-flops in FPU is gated. And the power consumption is saved up to 78.11% in FPU, corresponding to 17.02% power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in which the clock is controlled thoroughly and provided to FPU only when the FPU instruction is under-processing.
Keywords :
flip-flops; microprocessor chips; CPU; Dhrystone power consumption; SH-4A FPU core; clock gating technique; flip-flops; floating point unit; Benchmark testing; Correlation; Logic gates; Transforms;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
ISSN :
2162-7541
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
Type :
conf
DOI :
10.1109/ASICON.2011.6157117
Filename :
6157117
Link To Document :
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