An instruction set for a programmable signal processor dedicated to Viterbi detection

Author

Lou, Hui-Ling ; Cioffi, John M.

Author_Institution

Inf. Syst. Lab., Stanford Univ., CA, USA

fYear

1991

fDate

22-24 May 1991

Firstpage

247

Lastpage

251

Abstract

A programmable Viterbi signal processor (VSP) for the efficient implementation of sequence detection, most notably the Viterbi algorithm, is presented. The VSP architecture and instruction set introduced permits the efficient software implementation of decoders for most popular trellis codes, convolutional codes, and partial-response channels at rates ten to one hundred times faster than those achievable on conventional digital signal processors. Multidimensional trellis decoding can be implemented at sampling rates approaching 1 MHz in software on the VSP. The VSP contains three concurrent and independently programmable subprocessors. The architecture of the VSP is described. This paper´s emphasis is on the programming of the VSP

Keywords

binary sequences; convolutional codes; decoding; digital signal processing chips; trellis codes; VSP architecture; Viterbi detection; convolutional codes; instruction set; partial-response channels; programmable signal processor; sampling rates; sequence detection; subprocessors; trellis codes; trellis decoding; Computer architecture; Convolutional codes; Decoding; Digital signal processors; Information systems; Laboratories; Multidimensional systems; Signal processing; Signal sampling; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246672

Filename

246672