A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain

Author

Mao, Zhidong ; Chen, Liguang ; Wang, Yuan ; Lai, Jinmei

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

67

Lastpage

70

Abstract

A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2.5/3.3V Logic CMOS technology. The measured results show a correct function of 4/5-input LUT and a speedup in carry performance of nearly 3 times over current architecture.

Keywords

CMOS logic circuits; field programmable gate arrays; integrated circuit interconnections; table lookup; 1P8M logic CMOS technology; 4-input configurable LUT; 5-input configurable LUT; FPGA; configurable logic block; fast-path carry chain; interconnect structure; size 0.13 mum; slow-path carry chain; voltage 1.2 V; voltage 2.5 V; voltage 3.3 V; Silicon; Silicon compounds; 4/5-input LUT; FPGA; carry chain optimization; configurable logic block;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157124

Filename

6157124