Title :
A 768 Megapixels/sec inverse transform with hybrid architecture for multi-standard decoder
Author :
Ho, Tuan Minh Phan ; Le, Thang Minh ; Vu, Khanh Duy ; Mochizuki, Seiji ; Iwata, Kenichi ; Matsumoto, Keisuke ; Ueda, Hiroshi
Author_Institution :
Renesas Design Vietnam Co., Ltd., Ho Chi Minh City, Vietnam
Abstract :
This article introduces a fast hybrid architecture to perform the inverse transform for multiple standards including H.264/AVC, VC-1, MPEG-4, MPEG-2, H.263, and AVS. Both separated and common circuits are used in the hybrid architecture to get high throughput (768 Mpixel/sec for 8-point IDCT and 1536 Mpixel/sec for 4-point IDCT) while keep the area acceptable for many supported standards (56,989 logic gates @ 384 MHz). This hybrid architecture is also very expandable for future codec implementation. The design is described at RTL and synthesized using 130 nm cell library.
Keywords :
codecs; data compression; decoding; discrete cosine transforms; inverse transforms; media streaming; video coding; 4-point IDCT; 8-point IDCT; AVS; H.263; H.264-AVC; MPEG-2; MPEG-4; RTL design; VC-1; codec implementation; frequency 384 MHz; inverse transform; logic gates; multistandard decoder; size 130 nm; Decoding; Logic gates; Throughput; Transform coding; Hardware design; High throughput; Hybrid architecture; IDCT; Inverse Transform; Multi-codec;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157125
