Title :
A coarse-grained reconfigurable computing unit
Author :
Wang, Kanwen ; Chen, Shuai ; Cao, Wei ; Wang, Lingli ; Tong, Jiarong
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
Abstract :
This paper presents a 16-bit coarse-grained reconfigurable computing unit. It consists of computing part and interconnection part. The computing part includes adders/subtractors, shifters and complementers, whereas the interconnection part includes multiplexers. Apart from basic functions, it is capable of performing 1-output and 2-output constant multiplication, 4-input adder tree, absolute difference and butterfly operation. The implementation results show that the area is 2964 gates with the critical path of 18.24ns under 130-nm CMOS technology.
Keywords :
CMOS integrated circuits; adders; integrated circuit interconnections; multiplexing equipment; trees (mathematics); CMOS technology; adder tree; adders/subtractors; coarse-grained reconfigurable computing unit; complementers; interconnection part; multiplexers; shifters; size 130 nm; Adders; Cryptography; Registers; Coarse-grained; MCM; Reconfigurable Computing; SCM;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157129
