A Parallel Hardware Implementation for Motion Estimation for H.264/AVC Standard

Video compression requires high level of computation complexity at every stage especially motion estimation. Recent studies showed the motion estimation module consumes 97% of over all resources. Therefore, it is essential to embed these complex computationally intensive processes on a low power and low-cost single chip giving headway to multimedia systems. This paper demonstrates a hardware architecture, called ParallelMurf for efficient implementation of the Most Used Reference Frame Algorithm (MURFA). The result shows 89.3% improvement in execution time compared with the existing 2-D array structures for hardware implementation for motion estimation in H.264/AVC standard.