Analysis of NBTI-induced SNM degradation in power-gated SRAM cells

Temporal reliability degradation mechanism, and NBTI in particular, are especially critical for SRAM cells. In fact, unlike logic gates, which under some conditions can be forced into an NBTI-immune state, SRAM cells are always subject to aging, whatever value they are storing. In this work, we first quantify the aging, in terms of degradation of the signal-to-noise margin (SNM), of an SRAM cell as a function of the value stored in the cell, on a 45nm industrial technology. Then, we show how it is possible, by applying power gating to the memory cell, to further reduce the SNM degradation. Finally, we study the joint effect of power gating and bit control techniques.