ASIC implementation of an OFDM baseband transceiver for HINOC

Author

Chen, Hongming ; Chen, Xiaoyuan ; Liu, Tie ; Cheng, Yuhua

Author_Institution

Shanghai Res. Inst. of Microelectron. (SHRIME), Peking Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

167

Lastpage

170

Abstract

This paper describes the implementation of an area-efficient baseband transceiver using a conventional 1.2V, UMC 0.13μm Logic HS FSG process for HINOC communication systems. The novel scheme of channel training (CT) method based on beacon frame is proposed. The chip die size is 5.3 mm × 5.3 mm which fully integrated 2-channels ADC and 2-channels DAC. The data throughput in PHY layer achieves 97.44Mbps currently (1024 QAM modulation mode). Total power dissipation is 208.6mW with 3.3V power supply.

Keywords

OFDM modulation; analogue-digital conversion; application specific integrated circuits; digital-analogue conversion; quadrature amplitude modulation; transceivers; 2-channels DAC; ASIC implementation; HINOC communication systems; OFDM baseband transceiver; PHY layer; QAM modulation mode; UMC logic HS FSG process; area-efficient baseband transceiver; channel training; chip die size; data throughput; fully integrated 2-channels ADC; power 208 mW; power dissipation; size 0.13 mum; voltage 1.2 V; voltage 3.3 V; Baseband; Correlation; Indium phosphide; Modulation; Random access memory; Baseband; HINOC; OFDM; QAM;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157148

Filename

6157148