Title :
Circuit techniques for a wide world I/O path 64 Meg DRAM
Author :
Komatsuzaki, K. ; Sukegawa, S. ; Fung, K. ; Inui, T. ; Suzuki, T. ; Rountree, R. ; You, J. ; Borchers, B. ; Komatsuzaki, T. ; Shichijo, H. ; Tran, H. ; Scott, D.
Author_Institution :
Semicond. Process & Design Center, Texas Instrum. Inc., Dallas, TX, USA
Abstract :
The high rate data transfer between CPU and memory in future high performance systems requires the 64 Meg DRAM and generations beyond to take a new design approach. Fast RAS access time together with a wider I/O path are key DRAM performances indices for achieving high bandwidth CPU-MEMORY data operations. A novel Hierarchical Multi-Datalines (HMD) Architecture with a wide I/O path and high speed circuit design techniques used to implement this architecture in a 64 Meg DRAM are described
Keywords :
DRAM chips; memory architecture; 64 Mbit; DRAM; hierarchical multi-datalines architecture; high rate data transfer; high speed circuit design techniques; wide world I/O path; Bandwidth; Central Processing Unit; Circuit synthesis; Decoding; Delay; Differential amplifiers; Instruments; Process design; Random access memory; Signal restoration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-0036-X
DOI :
10.1109/VTSA.1991.246705
