Title :
A coded block adaptive neural network structure for pattern recognition VLSI
Author :
Kuo, J.B. ; Chen, Y.K. ; Lu, Y.H. ; Mao, W.C.
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A coded block adaptive neural network structure with a Hamming-Error-Correction-Technique (HECT), which can be used to greatly enhance the VLSI implementation capability of the block system using a parallel processor architecture is presented. According to simulation results, the coded block system with HECT provides a shorter learning time, and a better reconfigurability and an order-of-magnitude more efficient VLSI implementation capability
Keywords :
Hamming codes; VLSI; learning (artificial intelligence); parallel architectures; pattern recognition; self-organising feature maps; Hamming-Error-Correction-Technique; VLSI implementation capability; adaptive neural network structure; coded block; learning time; parallel processor architecture; pattern recognition VLSI; reconfigurability; Adaptive arrays; Adaptive systems; Data communication; Hardware; Neural networks; Neurons; Pattern recognition; Retina; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-0036-X
DOI :
10.1109/VTSA.1991.246707
