A NoC-based multi-core architecture for IEEE 802.11i CCMP

Author

Li, Yang ; Han, Jun ; Wang, Shuai ; Liu, Junbao ; Zeng, Xiaoyang

Author_Institution

State-Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

196

Lastpage

199

Abstract

To enhance security in WLAN, CCMP is introduced in IEEE 802.11i. This paper presents a heterogeneous multi-core architecture based on NoC to support high-speed CCMP application. Four general processors and twelve security ASIPs are connected by a 4×4 mesh NoC. A modified PTLU is implemented in each ASIP to accelerate AES operations. Task parallelism in CCMP is exploited to obtain high throughput. Synthesized in SMIC 0.13μm CMOS technology, the proposed system measures a hardware cost of 3.08M gates. Experiment results show that the system achieves a throughput of 787Mbps at 84MHz.

Keywords

CMOS integrated circuits; access protocols; cryptography; network-on-chip; table lookup; wireless LAN; AES operations; CBC-MAC protocol; IEEE 802.11i CCMP; NoC-based multicore architecture; SMIC CMOS technology; WLAN security; advanced encryption standard; application-specific instruction set processor; general processors; heterogeneous multicore architecture; high-speed CCMP application; modified PTLU; parallel table look-up; security ASIP; size 0.13 mum; task parallelism; Application specific integrated circuits; Cryptography; Encapsulation; Pipelines; Standards; Throughput; CCMP; IEEE 802.11i; Multi-Core; NoC;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157155

Filename

6157155