A channel estimator for LTE downlink mapped on a multi-core processor platform

Author

He, Maofei ; Zhang, Jiajie ; Fan, Wenhua ; Yu, Zhiyi ; Zeng, Xiaoyang

Author_Institution

State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China

fYear

2011

fDate

25-28 Oct. 2011

Firstpage

204

Lastpage

207

Abstract

This paper presents an implementation of channel estimation for LTE downlink MIMO system on a multi-core processor platform. With the development of wireless communication, it is gradually difficult for ASIC baseband processing solutions to adapt the rapidly changing communication requirements. Multi-core solution for communication applications arises due to its programmability and reconfigurability. The multi-core processor platform is a mesh array of SIMD cores which is well suited for communication applications. A channel estimator with the throughput of 113.5Msymbol/s is realized by fully utilizing task-level parallelism, data-level parallelism and pipeline structure on multi-core processor platform.

Keywords

Long Term Evolution; application specific integrated circuits; channel estimation; multiprocessing systems; parallel processing; ASIC baseband processing; LTE downlink MIMO system; SIMD cores; channel estimator; data-level parallelism; multicore processor platform; pipeline structure; task-level parallelism; wireless communication; Assembly; Interpolation; OFDM; Signal to noise ratio; Switches; TV; Time frequency analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC (ASICON), 2011 IEEE 9th International Conference on

Conference_Location

Xiamen

ISSN

2162-7541

Print_ISBN

978-1-61284-192-2

Electronic_ISBN

2162-7541

Type

conf

DOI

10.1109/ASICON.2011.6157157

Filename

6157157