Misfit stress in p/p+ epitaxial silicon wafers: effect and elimination

Author

Lin, Wen ; Hill, D.W. ; Paulnack, C.L. ; Kelly, M.J.

Author_Institution

AT&T Bell Labs., Allentown, PA, USA

fYear

1991

fDate

22-24 May 1991

Firstpage

57

Lastpage

60

Abstract

A large lattice mismatch occurs when lightly boron doped (E15 cm ^-3) epitaxial silicon layers are deposited on a heavily boron doped (E19 cm^-3) substrate. The misfit stress causes wafer bow and the formation of misfit dislocations at the interface. The structure of misfit dislocation and effect of misfit stress on p/p+ wafer processing are discussed. A method for elimination of the misfit stress in p/p+ silicon wafers via lattice compensation is presented

Keywords

annealing; boron; dislocation structure; elemental semiconductors; interface structure; semiconductor doping; semiconductor epitaxial layers; semiconductor growth; silicon; stress relaxation; vapour phase epitaxial growth; CVD; Si:B epitaxial wafers; Si:B substrate; Si:B,Ge; ULSI; VLSI; counter-doping; elemental semiconductor; heavily doped substrate; lattice compensation; lattice mismatch; lightly doped layers; misfit dislocations; misfit stress; p/p+ wafer processing; wafer bow; Boron; Compressive stress; Doping; Epitaxial layers; Lattices; Silicon; Substrates; Temperature; Tensile stress; Thermal stresses;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on

Conference_Location

Taipei

ISSN

1524-766X

Print_ISBN

0-7803-0036-X

Type

conf

DOI

10.1109/VTSA.1991.246712

Filename

246712