Title :
Pits reduction for poly Buffer LOCOS in VLSI fabrication
Author :
Su, W.D. ; Lee, Paul P J ; Chang, C.C. ; Cheng, C.H.
Author_Institution :
Dept. of Adv. Technol. Dev., ERSO, ITRI, Hsinchu, Taiwan
Abstract :
Gate oxide and junction integrity are the major concerns for the application of Poly-Buffer LOCOS in VLSI manufacturing. The authors observed that nonsuitable removal of nitride and poly silicon will induce pits around the corner of bird´s peak region, and will degrade the gate oxide integrity. Tight control and optimization of the process solve this problem
Keywords :
VLSI; elemental semiconductors; integrated circuit technology; oxidation; semiconductor technology; silicon; Si; Si-SiO2-Si3N4; VLSI fabrication; bird´s peak region; elemental semiconductor; gate oxide integrity; junction integrity; optimization; pits reduction; poly Buffer LOCOS; Etching; Fabrication; Large scale integration; Manufacturing; Oxidation; Semiconductor films; Silicon; Stress; Thickness control; Very large scale integration;
Conference_Titel :
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location :
Taipei
Print_ISBN :
0-7803-0036-X
DOI :
10.1109/VTSA.1991.246715
