Title :
Towards the next generation of low-power test technologies
Author_Institution :
Dept. of Comput. Syst. & Eng., Kyushu Inst. of Technol., Iizuka, Japan
Abstract :
This paper first describes the basics of VLSI testing and the impact of test power. It then reviews the current status of low-power testing. It further highlights the needs for the next generation of low-power test technologies, which are critical for low-power devices in the deep submicron era.
Keywords :
VLSI; integrated circuit testing; low-power electronics; VLSI testing; deep submicron era; impact; low-power device; low-power test technology; low-power testing; next generation; test power;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157164
