• DocumentCode
    3380575
  • Title

    A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

  • Author

    Kim, Daeik D. ; Cho, Choongyeun ; Kim, Jonghae ; Plouchart, Jean-Olivier ; Lim, Daihyun

  • Author_Institution
    IBM SRDC, Hopewell Junction, NY
  • fYear
    2008
  • fDate
    12-15 Oct. 2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 5-stage CML prescaler operating up to 84 GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.40 power-delay product per gate. The prescaler´s phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.
  • Keywords
    CMOS integrated circuits; low-power electronics; millimetre wave circuits; prescalers; SOI CMOS technology; low-power mmWave CML Prescaler; power 17.7 mW; voltage 1.8 V; CMOS process; CMOS technology; Frequency conversion; Millimeter wave communication; Phase locked loops; Phase noise; Time measurement; Topology; Vehicle dynamics; Voltage-controlled oscillators;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Compound Semiconductor Integrated Circuits Symposium, 2008. CSIC '08. IEEE
  • Conference_Location
    Monterey, CA
  • ISSN
    1550-8781
  • Print_ISBN
    978-1-4244-1939-5
  • Electronic_ISBN
    1550-8781
  • Type

    conf

  • DOI
    10.1109/CSICS.2008.50
  • Filename
    4674505
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3380575