A new scheme for testability improvement of ECC incorporated memory

With the technology node going to the nanometer region, the chips, especially the memory parts, face a huge challenge in the reliability. The error-correcting code (ECC) is a traditional way to improve the chips´ reliability; however, it has a problem that the memory with ECC attached is difficult to be test in normal lab situation. To solve this problem, we design a new scheme for the input part of the memory to enable a “wrong” check bits to be inputted into the memory. The chips using this method have been taped out and the test results show that their testability have been increased with little harm to the performance in other aspects.