Title :
A BIST scheme for high-speed Gain Cell eDRAM
Author :
Yan, Bing ; Xie, Yufeng ; Yuan, Rui ; Lin, Yinyin
Author_Institution :
Dept. of Microelectron., Fudan Univ., Shanghai, China
Abstract :
A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4-stage pipeline for instruction execution makes at-speed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13μm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.
Keywords :
CMOS integrated circuits; DRAM chips; automatic test equipment; built-in self test; instruction sets; silicon; 4-stage pipeline; ATE; BIST scheme; CMOS technology; Si; at-speed test; built-in self-test; embedded DRAM; frequency 200 MHz; high-speed gain cell eDRAM; instruction execution; instruction set architecture; refresh test; silicon measurement; single-address test; size 0.13 mum; traversal test; Application specific integrated circuits; Built-in self-test; Clocks; Random access memory; Silicon;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157167
