A radix-4 single-precision floating point divider based on digit set interleaving

Today, high-performance divider implementations almost always use the classical SRT algorithm in conjunction with a redundant residual representation like carry-save. In this paper, a modified approach is presented, which reduces the number of comparisons inside the quotient digit selection function (QDSF) to the number necessary in a non-redundant implementation of the same radix. To keep the overlap in the QDSF needed to support residual redundancy, the reliability of sign estimations can be detected, which is less complex in terms of hardware. The reliability information is used to switch between two interleaved digit sets for quotient representation, which, in superposition, form a digit set with maximum redundancy. A radix-4 single-precision floating point divider using the proposed algorithm was synthesized using a low power 65-nm CMOS library. The result exhibits an extremely low area in combination with an attractive cycle time and power dissipation.