A novel two quadrant MOS translinear Squarer-divider cell

A novel two quadrant low-voltage current-mode squarer/divider circuit is presented. The circuit is based on a CMOS translinear loop using a novel biasing scheme that allows class-AB operation. Owing to this fact the circuit can drive current signals in two quadrants. The proposed cell can operate properly with supply voltages as low as V_GS ^+2V _DSsat and efficient power consumption. Measurement results from a fabricated prototype in a 0.8 mum CMOS technology occupying an area of 100 mum times 70 mum, demonstrate the correct operation of the circuit with a supply voltage of 1.5 V and a power consumption of 150 muW.