A high performance pseudo-multi-core ECC processor over GF(2163)

In this paper, we propose a high performance processor for elliptic curve cryptography (ECC) over GF(2¹⁶³) by using polynomial presentation. It has three finite field (FF) RISC cores and a main controller to achieve instruction-level parallelism (ILP) with pipeline so that the largely parallelized algorithm for elliptic curve point multiplication can be well suited on this platform. Instructions for combined FF operation are proposed to decrease clock cycles in the instruction set. The interconnection among three FF cores and the main controller is obtained by analyzing the data dependency in the parallelized algorithm. The whole design is implemented on Xilinx XC4VLX80 FPGA device, and it can reach 185 MHz with 20,807 slices. The total time required for one ECC point scalar operation is 7.7μs in 1428 cycles.