DocumentCode :
3380868
Title :
High Linearity 0.18μm CMOS Mixer with Current Draining Technique
Author :
Ramiah, Hairkrishnan ; Zulklifli, Tun Zainal Azni
Author_Institution :
Sch. of Electr. & Electron. Eng., Univ. Sains Malaysia, Penang
fYear :
2005
fDate :
21-24 Nov. 2005
Firstpage :
1
Lastpage :
5
Abstract :
The drive for cost reduction has led to the use of CMOS technology for highly integrated radios. This paper presents a new CMOS active mixer topology with current draining features, to reduce flicker noise effect. Mixing is achieved by exploiting two transconductors with cross coupled outputs, which are alternatingly activated by the current commutating CMOS switches. The architecture can operate at low supply voltage by the use of switches exclusively connected to supply voltages. Realized in 0.18 μm CMOS technology and operating from 1.8 V power supply, the design consumes 3 mW of power. The mixer exhibits a third order input intercept point (IIP3) of better than 17 dBm. An overall noise figure of 18 dB is achieved at 100 kHz. The mixer also shows an input dynamic range performance of 5.8 dBm, with -150.3 dB carrier feedthrough suppression.
Keywords :
CMOS integrated circuits; circuit noise; flicker noise; mixers (circuits); network topology; CMOS active mixer topology; CMOS switches; CMOS technology; carrier feedthrough suppression; current draining technique; flicker noise effect; input dynamic range performance; noise figure 18 dB; power 3 mW; size 0.18 mum; third order input intercept point; transconductors; voltage 1.8 V; 1f noise; CMOS technology; Costs; Linearity; Low voltage; Noise figure; Power supplies; Switches; Topology; Transconductors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
TENCON 2005 2005 IEEE Region 10
Conference_Location :
Melbourne, Qld.
Print_ISBN :
0-7803-9311-2
Electronic_ISBN :
0-7803-9312-0
Type :
conf
DOI :
10.1109/TENCON.2005.301324
Filename :
4085124
Link To Document :
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