Title :
Word line boost and read SA PMOS compensation (SAPC) for ROM in 55nm CMOS
Author :
Huang, Ruifeng ; Zheng, Jianbin ; Zhang, Lijun ; Zhang, Zhaoyong ; Wu, Hao ; Yu, Yue
Author_Institution :
Aicestar Technol. Corp., Suzhou, China
Abstract :
This paper presents circuit techniques to improve read capability for single-end SA ROM design fabricated in UMC 55nm process. DV0 and DV1 margin are key features reflect read capability, and result show that DV0 enhanced significantly by using WL boosting schemes and DV1 enhanced by SA PMOS compensation (SAPC) structure. Combining WL boosting and SAPC technologies, the read fail problem in ROM could be solved easily which bring by leakages especially under 60nm process.
Keywords :
CMOS analogue integrated circuits; amplifiers; integrated circuit design; read-only storage; CMOS process; DV0 margin; DV1 margin; SA PMOS compensation; SAPC; UMC process; WL boosting schemes; circuit techniques; read only memories; single-end SA ROM design; single-end sensitive amplifier ROM design; size 55 nm; size 60 nm; word line boost technology;
Conference_Titel :
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location :
Xiamen
Print_ISBN :
978-1-61284-192-2
Electronic_ISBN :
2162-7541
DOI :
10.1109/ASICON.2011.6157183
