VLSI interconnect delay analysis method for ramp input signal

Many methods for VLSI interconnect delay analysis based on the transfer function have been developed instead of differential equation base circuit analysis. This paper proposes transfer function base method named DPW. DPW employs conventional Weibull distribution method, but we modified it to cope with ramp form driver output signal calculated by popular effective capacitance base gate modeler. This proposal method yields very high accuracy compared with conventional Weibull distribution method. Experimental results are presented using industrial VLSI design data.