Wafer-scale systolic array for adaptive antenna processing

The wafer-scale VLSI system determines the weights for an adaptive antenna application. The data are sampled N-component vector time series X_(n), whose components are time functions observed at N individual antenna ports. The processed output, y(n), is a weighted sum of the components, e.g., W_^tX_(n). The authors expect to compute W_ about 150 times per second, based on observations of many exponentially windowed samples of X_ which arrive much more frequently, about 45000 times per second. The algorithm for determining W_ is based on the use of Givens transformations to rotate the original data into a lower triangular set of linear equations. The computational cost of this algorithm increases with N, the number of degrees of freedom, as N³. For sufficiently large N, one must employ some degree of parallelism. The advanced architecture uses ^N/₂ processors connected in a linear chain, suitable for realizing this algorithm for N=64 in a systolic VLSI wafer-scale design