RRA-based multi-objective optimization to mitigate the worst cases of placement

As VLSI/PCB design keeps going through higher complexity, it is increasingly important to mitigate the worst cases of placement in physical design in order to get an acceptable solution within shorter runtime. This paper mainly focuses on the worst-case mitigation for multi-objective placement by using relay-race algorithm (RRA). Several intuitive advantages of RRA are discussed by comparing with simulated annealing (SA) and genetic algorithm (GA). MCNC and ami49_X benchmarks are used to test the effectiveness of RRA for placement with multiple objectives. Based on the experimental data comparing with SA, RRA obtains near 24% worst-case improvement for interconnect power consumption on average without any degradation of maximal delay. With respect to area minimization, RRA gets worst-case improvement for all tested benchmarks with near 50% runtime of SA (2X speedup).