Numerical characterization of multi-dielectric green´s function for floating random walk based capacitance extraction

The floating random walk (FRW) algorithm has several advantages for extracting interconnect capacitance. However, for multi-layer dielectrics in VLSI technology, the efficiency of FRW algorithm would be degraded due to the frequent stop of walk at dielectric interface. In this paper, an approach is proposed to calculate multi-dielectric Green´s function, which is utilized to enable hops across dielectric interface in the FRW. Numerical results show that the proposed approach is about 4X faster than an existing method, and brings several times speedup to the FRW-based capacitance extraction for actual multi-dielectric interconnect structures.