DocumentCode
3381184
Title
A new pseudo-exhaustive test method
Author
Wang, Jhing-Fa ; Wang, Wei-Lun ; Tien, Tzyy-Kuen
Author_Institution
Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
fYear
1991
fDate
22-24 May 1991
Firstpage
414
Lastpage
418
Abstract
An efficient and systematic pseudo-exhaustive test pattern generation algorithm has been proposed in this paper to solve the problem of test generation in BIST. The algorithm has the following advantages: (1) it requires a minimum number of test signals for testing a circuit (2) it executes quickly with polynomial time complexity (3) it requires fewer test patterns and low hardware cost compared to five previous proposed methods
Keywords
automatic testing; built-in self test; logic testing; BIST; hardware cost; polynomial time complexity; pseudo-exhaustive test method; test pattern generation algorithm; test signals; Automatic testing; Built-in self-test; Circuit testing; Costs; Counting circuits; Design methodology; Flip-flops; Hardware; System testing; Terminology;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246752
Filename
246752
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