DocumentCode
3381220
Title
An event-driven incremental timing fault simulator
Author
Jou, Shyh-Jye ; Shen, WenZen ; Chiou, Shwu-Huey
Author_Institution
Dept. of Electr. Eng., Nat. Central Univ., Taipei, Taiwan
fYear
1991
fDate
22-24 May 1991
Firstpage
424
Lastpage
427
Abstract
An efficient MOS multiple sets of multiple faults simulator with electrical timing information is presented. By using event-driven, selective trace and mixed incremental-in-space, signal and time simulation techniques, the simulation results show that it is superior in speedup, extra memory used and precision to other approaches. Moreover, this simulator is suited for parallel simulation in a multiprocessor system
Keywords
MOS integrated circuits; VLSI; circuit CAD; digital simulation; fault location; mixed analogue-digital integrated circuits; MOS multiple sets; electrical timing information; event-driven incremental timing fault simulator; incremental-in-space; memory; parallel simulation; precision; selective trace; time simulation; Circuit faults; Circuit simulation; Computational modeling; Degradation; Discrete event simulation; Logic circuits; MOS devices; Switches; Threshold voltage; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems, and Applications, 1991. Proceedings of Technical Papers, 1991 International Symposium on
Conference_Location
Taipei
ISSN
1524-766X
Print_ISBN
0-7803-0036-X
Type
conf
DOI
10.1109/VTSA.1991.246754
Filename
246754
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