Title :
Fault collapsing with linear complexity in digital circuits
Author :
Ubar, R. ; Mironov, D. ; Raik, J. ; Jutman, A.
Author_Institution :
Dept. of Comput. Eng., TTU, Tallinn, Estonia
fDate :
May 30 2010-June 2 2010
Abstract :
The paper presents a new structural fault-independent fault collapsing method for test generation based on the topology analysis of the circuit, which has linear complexity. Fault collapsing is carried out by superposition of binary decision diagrams (BDD) for logic gates, which is used for constructing structurally synthesized BDDs (SSBDD). A new class of SSBDDs with multiple inputs (SSMIBDD) is proposed to reduce the size of collapsed fault sets. Experimental data show that the fault collapsing by the proposed method is more efficient than other strucural fault collapsing methods with comparative time cost are.
Keywords :
combinational circuits; decision diagrams; fault diagnosis; logic gates; logic testing; binary decision diagrams; combinational circuits; digital circuits; fault equivalence; linear complexity; logic gates; structural fault independent fault collapsing method; test generation; Binary decision diagrams; Boolean functions; Circuit analysis; Circuit faults; Circuit synthesis; Circuit testing; Circuit topology; Data structures; Digital circuits; Logic gates; BDDs; combinational circuits; fault collapsing; fault equivalence and dominance; test generation;
Conference_Titel :
Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on
Conference_Location :
Paris
Print_ISBN :
978-1-4244-5308-5
Electronic_ISBN :
978-1-4244-5309-2
DOI :
10.1109/ISCAS.2010.5537504
