Automatic layout generator for embedded FPGA cores

There is a growing tendency for FPGA (Field Programmable Gate Array) IP (Intellectual Property) cores to be embedded in an SOC (System On a Chip). The embedded FPGA cores can improve the flexibility of the SOC chip. However, different SOC varies in the demands on the scale of FPGA tile array. Therefore, a scalable FPGA generator is required. In this paper, an automatic layout generator to support user-defined FPGA array size is introduced and compared with the previous related works. This paper shows that the proposed layout generator based on FPGA tiles is more practical than the previous tools.