Limit cycle behavior in a class-AB second-order square root domain filter

This paper presents a second-order CMOS companding filter that exhibits a limit cycle. The filter employs the quasi-quadratic law of the MOS transistor in strong inversion and saturation to achieve compression together with a Class-AB topology to extend the dynamic range. In the zero-input case, the filter operates in the manner expected of an externally-linear circuit. However, when a standard linear IC design technique is applied to it, unwanted zero-input sustained oscillations may be observed. Simulations and measurement results from a semi-custom realization in a 0.8 mum CMOS process are used to explore this behavior.