DocumentCode :
3381394
Title :
Bias Temperature Instability model for digital circuits - predicting instantaneous FET response
Author :
Bansal, Aditya ; Zhao, Kai ; Kim, Jae-Joon ; Rao, Rahul
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear :
2011
fDate :
10-14 April 2011
Abstract :
We propose a semi-empirically enhanced BTI model to predict the instantaneous shift in VT due to both NBTI (in PFETs) and PBTI (in NFETs). Our proposed model uses same technology parameters as in existing model, and applied for both NBTI and PBTI. At every step of model generation, we demonstrate the correlation between our model and measured hardware. Further, we discuss the necessary steps to integrate our model with existing digital circuit simulators.
Keywords :
digital circuits; field effect transistors; semiconductor device models; NBTI; NFET; PBTI; PFET; digital circuit simulators; instantaneous FET response; negative bias temperature instability model; positive bias temperature instability model; semiempirically enhanced BTI model; Computational modeling; Data models; Degradation; FETs; Integrated circuit modeling; Predictive models; Stress;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
ISSN :
1541-7026
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
Type :
conf
DOI :
10.1109/IRPS.2011.5784560
Filename :
5784560
Link To Document :
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