A chip design for binary and binary morphological operations

Author

Shaaban, Khaled M. ; Ali, Samia A. ; Mahdy, Yousf B.

Author_Institution

Dept. of Electr. Eng., Assiut Univ., Egypt

fYear

1999

fDate

1999

Firstpage

554

Lastpage

559

Abstract

A design for a chip to perform binary and binary morphological operations is provided. The chip is intended to be a part of a pipeline machine controlled by a general purpose processor. It could process 25512×512 pixel frames per second in one pixel per clock cycle rate. In real time application an array of this chip could be used, leading to a less expensive design than using an array of general DSP chips. The functionality of the chip is programmable by changing the flow of data between the internal units using a multiplexer and demultiplexer set. A 15-bit control register is used to set the flow path and consequently the operation

Keywords

algebra; digital signal processing chips; geometry; mathematical morphology; pipeline processing; real-time systems; 15-bit control register; binary morphological operations; binary operations; chip design; clock cycle rate; demultiplexer; flow path; general DSP chips; general purpose processor; internal units; multiplexer; pipeline machine; pixel frames; real time application; Arithmetic; Chip scale packaging; Computer vision; Digital signal processing chips; Electronic switching systems; Hip; Image analysis; Morphological operations; Morphology; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Intelligence and Systems, 1999. Proceedings. 1999 International Conference on

Conference_Location

Bethesda, MD

Print_ISBN

0-7695-0446-9

Type

conf

DOI

10.1109/ICIIS.1999.810346

Filename

810346