Title :
The impact of RTN on performance fluctuation in CMOS logic circuits
Author :
Ito, Kyosuke ; Matsumoto, Takashi ; Nishizawa, Shinichi ; Sunagawa, Hiroki ; Kobayashi, Kazutoshi ; Onodera, Hidetoshi
Author_Institution :
Kyoto Univ., Kyoto, Japan
Abstract :
In this paper, the impact of Random Telegraph Noise (RTN) on CMOS logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of a sequential logic gate under low voltage operation.
Keywords :
CMOS logic circuits; logic gates; sequential circuits; CMOS logic circuits; circuit matrix array; low voltage operation; performance fluctuation; random telegraph noise; sequential logic gate; size 65 nm; Delay; Frequency conversion; Low voltage; Noise; Oscillators; Time frequency analysis;
Conference_Titel :
Reliability Physics Symposium (IRPS), 2011 IEEE International
Conference_Location :
Monterey, CA
Print_ISBN :
978-1-4244-9113-1
Electronic_ISBN :
1541-7026
DOI :
10.1109/IRPS.2011.5784563
