DocumentCode
3381456
Title
CPIPQ: A common platform for silicon IP qualification
Author
Mok, Mark P C ; Lo, Kenneth C K ; Jiao, Yuzhong ; Li, Yiu Kei
Author_Institution
IC Design Group, Hong Kong Appl. Sci. & Technol. Res. Inst. (ASTRI), Hong Kong, China
fYear
2011
fDate
25-28 Oct. 2011
Firstpage
405
Lastpage
408
Abstract
With the increasing complexity of system-on-chip (SoC) design, intellectual property (IP)-based design flow is becoming an inevitable trend to achieve high performance and short time-to-market. However the transfer of IP core remains a complex and time-consuming process. Different IP vendors usually use different design rules and tool flows, which make it difficult for IP integrators to select suitable IP cores and integrate them rapidly. In this paper, a common platform for IP qualification (CPIPQ) is presented to provide and establish a set of common standards to qualify Soft/Hard IP. There are two kinds of qualification methods: subjective quality metric and objective quality metric. We use IEEE QIP Metric to evaluate the subjective quality metrics of IP cores. Objective metrics are measured automatically by using commercial EDA tools, as well as tools that developed by ASTRI IC Design Group.
Keywords
electronic design automation; elemental semiconductors; logic circuits; microprocessor chips; silicon; system-on-chip; ASTRI IC Design Group; CPIPQ; EDA tools; IEEE QIP metric; IP core; IP integrators; IP vendors; Si; common platform; intellectual property design flow; objective quality metric; short time-to-market; silicon IP qualification; soft/hard IP; subjective quality metric; system-on-chip; Qualifications;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC (ASICON), 2011 IEEE 9th International Conference on
Conference_Location
Xiamen
ISSN
2162-7541
Print_ISBN
978-1-61284-192-2
Electronic_ISBN
2162-7541
Type
conf
DOI
10.1109/ASICON.2011.6157207
Filename
6157207
Link To Document